1. Field of the Invention
The present invention generally relates to a pipelined analog-to-digital converter (ADC), and more particularly to a conditional capacitor averaging circuit and method for reducing nonlinearity induced by capacitor mismatch in the pipelined ADC.
2. Description of Related Art
The accuracy of a pipelined analog-to-digital converter (ADC) is mainly limited by capacitor mismatch due to the fact that the fabricated capacitor accuracy is commonly limited to 10-11 bit level. Some techniques are disclosed to reduce nonlinearity, e.g., differential nonlinearity (DNL) and integral nonlinearity (INL), induced by the capacitor mismatch. However, the conventional techniques either cannot effectively improve the nonlinearity or cannot be adapted to various kinds of ADCs. For example, most of the conventional techniques are only suitable for 1-bit or 1.5-bit/stage architectures, but not the 2.5-bit/stage architecture that is demonstrated as one of the most power-efficient architectures.
Although some techniques have been disclosed that can be applied for architectures with any stage resolutions, those techniques, however, require sophisticated circuit or complex switching networks.
For the foregoing reasons, a need has arisen to propose a novel scheme for reducing the error effect induced by capacitor mismatch, particularly in 2.5-bit/stage high-resolution pipelined ADCs, to achieve more power-efficient conversion while maintaining sufficient static and dynamic performances.